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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P068
4 BIT SINGLE-CHIP MICROCOMPUTER
The PD75P068 is produced by replacing the internal mask ROM of the PD75068 with a one-time PROM in which data can be written once. The following user's manual describes the details of the functions of the PD75P068. Be sure to read it before designing an application system.
PD75068 User's Manual: IEU-1366
FEATURES * Compatible with the PD75068
* Can be replaced with the PD75068 containing mask ROM on a full-production basis.
* * * * *
Internal one-time PROM: 8064 words x 8 bits Internal RAM: 512 words x 4 bits Internal pull-up resistors can be specified with software: Ports 0 to 3 and 6 N-ch open-drain input-output: Ports 4 and 5 Can operate at low voltage: VDD = 2.7 to 6.0 V
ORDERING INFORMATION
Part number Package 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (Square 10 mm) Quality grade Standard Standard
PD75P068CU PD75P068GB-3B4
Caution The PD75P068 is not provided with mask-selected pull-up resistors.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. IC-3290A (O.D. No. IC-8623A Date Published April 1994 P Printed in Japan Major changes in this revision are indicated by stars (5) in the margins.
1990 (c) NEC CORPORATION 1993
PD75P068
PIN CONFIGURATION (TOP VIEW)
* 42-pin plastic shrink DIP
XT1 XT2 RESET X1 X2 MD3/P33 MD2/P32 MD1/P31 MD0/P30 AVSS AN7/KR3/P63 AN6/KR2/P62 AN5/KR1/P61 AN4/KR0/P60 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVREF VPP VDD 1 2 3 4 5 6 7 8 42 41 40 39 38 37 36 35 VSS P40 P41 P42 P43 P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/INT2 P13/ TI0 P20/PTO0 P21 P22/PCL P23/BUZ
PD75P068CU
9 10 11 12 13 14 15 16 17 18 19 20 21
34 33 32 31 30 29 28 27 26 25 24 23 22
* 44-pin plastic QFP
P20/PTO0 P110/AN0 P111/AN1 P23/BUZ P22/PCL P13/ TI0
AVREF
P21
VDD
INT2/P12 INT1/P11 INT0/P10 SB1/SI/P03 SB0/SO/P02 SCK /P01 INT4/P00 P53 P52 P51 P50
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VPP
NC
P112 /AN2 P113/AN3 P60/KR0/AN4 P61/KR1/AN5 P62/KR2/AN6 P63/KR3/AN7 AVSS P30/MD0 P31/MD1 P32/MD2 P33/MD3
PD75P068GB-3B4
28 27 26 25 24
23 12 13 14 15 16 17 18 19 20 21 22
RESET
P43
P42
P41
P40
XT1
XT2
NC
VSS
X1
2
X2
BLOCK DIAGRAM
Basic interval timer INTBT TI0/P13 PTO0/P20 Timer/ counter #0 INTT0 SI/SB1/P03 SO/SB0/P02 SCK/P01 Serial interface INTCSI INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0-KR3/P60-P63 4 Program counter (13) ALU CY
Bit sequential buffer
Port 0 SP Port 1 Bank Port 2
4
P00-P03
4
P10-P13
4
P20-P23
Port 3
4
P30/MD0-P33/MD3
General register Interrupt control PROM program memory 8064 x 8 bits Watch timer INTW
Port 4
4
P40-P43
Port 5
4
P50-P53
BUZ/P23
Decode and control
Port 6 RAM data memory 512 x 4 bits
4
P60-P63
Port 11
4
P110-P113
AVREF AVSS AN0-AN3/P110-P113 AN4-AN7/P60-P63 8
A/D converter
fX/2N Clock output Clock divider control Clock generator Sub Main
CPU clock Stand by control
PD75P068
PCL/P22
XT1 XT2
X1
X2
3
VPP
VDD
VSS RESET
PD75P068
CONTENTS 1. PIN FUNCTIONS ........................................................................................................................
1.1 PORT PINS .......................................................................................................................................... 1.2 NON-PORT PINS ................................................................................................................................ 1.3 PIN INPUT/OUTPUT CIRCUITS ........................................................................................................
5
5 6 7
2. 3.
DIFFERENCE BETWEEN THE PD75P068 AND PD75068 ................................................... WRITING TO AND VERIFYING PROM (PROGRAM MEMORY) ............................................
3.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY ......... 3.2 WRITING TO THE PROGRAM MEMORY ......................................................................................... 3.3 READING THE PROGRAM MEMORY ..............................................................................................
9 10
10 11 12
5
4. 5.
SCREENING ONE-TIME PROM PRODUCTS ........................................................................... ELECTRICAL CHARACTERISTICS ............................................................................................. CHARACTERISTIC CURVES (FOR REFERENCE) ..................................................................... PACKAGE DRAWINGS .............................................................................................................. RECOMMENDED SOLDERING CONDITIONS .......................................................................
13 14 27 33 35 36 37
5
6. 7.
5
8.
APPENDIX A DEVELOPMENT TOOLS.......................................................................................... APPENDIX B RELATED DOCUMENTS ..........................................................................................
4
PD75P068
1.
1.1
PIN FUNCTIONS
PORT PINS
Input/ output Input I/O I/O I/O 8 bit I/O I/O circuit typeNote 1 B x Input F -A F -B M -C With noise elimination function 4-bit input port (PORT1). Pull-up resistors can be provided by software in units of 4 bits. 4-bit I/O port (PORT2). Pull-up resistors can be provided by software in units of 4 bits. x Input B -C
Pin P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30Note 2 P31Note 2 P32Note 2 P33Note 2
Shared pin INT4 SCK SO/SB0 SI/SB1 INT0
Function 4-bit input port (PORT0). For P01-P03, pull-up resistors can be provided by software in units of 3 bits.
When reset
Input
INT1 INT2 TI0 PTO0
I/O
-- PCL BUZ MD0
x
Input
E-B
I/O
MD1 MD2 MD3
Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. N-ch open-drain 4-bit I/O port (PORT4). Withstand voltage of 10 V Data input-output (low-order 4 bits) when writing to and verifying program memory (PROM) N-ch open-drain 4-bit I/O port (PORT5). Withstand voltage of 10 V Data input-output (high-order 4 bits) when writing to and verifying program memory (PROM) Programmable 4-bit I/O port (PORT6). Pull-up resistors can be provided by software in units of 4 bits.
x
Input
E-B
P40-P43Note 2
I/O
--
High Impedance q High Impedance
M-A
P50-P53Note 2
I/O
--
M-A
P60 P61 P62 P63 P110 P111 P112 P113 Input I/O
KR0/AN4 KR1/AN5 KR2/AN6 KR3/AN7 AN0 AN1 AN2 AN3
x
Input
Y -D
4-bit input port (PORT11) x Input Y-A
Notes 1. The circle (q ) indicates the Schmitt trigger input. q 2. Can directly drive the LED.
5
PD75P068
1.2 NON-PORT PINS
Input/ output Input I/O I/O I/O I/O I/O I/O Input Input I/O circuit typeNote 1 B -C E-B E-B E-B F -A F -B M -C B B -C
Pin
Shared pin
Function Input for receiving external event pulse signal for timer/event counter Timer/event counter output Clock output Output for arbitrary frequency output (for buzzer output or system clock trimming) Serial clock I/O Serial data output Serial bus I/O Serial data input Serial bus I/O Edge detection vectored interrupt input (either rising edge or falling edge detection) Edge detection vectored interrupt input (detection edge selectable) Edge detection testable input (rising edge detection) Parallel falling edge detection testable input
When reset
TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0-KR3 AN0-AN3 AN4-AN7 AVREF AVSS
P13 P20 P22 P23 P01 P02 P03 P00 P10 P11
Input Input Input Input Input Input Input Input Input
Input I/O Input I/O Input --
P12 P60-P63/ AN4-AN7 P110-P113 P60-P63/ KR0-KR3 -- --
Input Input
B -C Y -D Y-A
8-bit analog input For A/D converter only Reference voltage input GND potential Crystal/ceramic connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1, and its reverse phase signal is applied to XT2. XT1 can be used as a 1-bit input (test). System reset input Mode selection when writing to or verifying program memory (PROM) Programming voltage application when writing to or verifying program memory (PROM) Directly connected to VDD during normal operation. +12.5 V is applied when data is written in PROM or when the PROM is verified. Main power supply GND potential
-- -- --
Y -D Z Z
X1, X2
Input
--
--
--
XT1, XT2
Input
--
--
--
RESET MD0-MD3
Input I/O
-- P30-P33
-- Input
B E-B
VPPNote 2
--
--
--
--
VDD VSS
-- --
-- --
-- --
-- --
Notes 1. The circle (q ) indicates the Schmitt trigger input. q 2. Unless the VPP pin is directly connected to the VDD pin during normal operation, the
PD75P068 does not operate normally.
6
PD75P068
1.3 PIN INPUT/OUTPUT CIRCUITS (1/3)
Type A (For type E-B) Type D (For type E-B,F-A)
The input/output circuit of each PD75P068 pin is shown below in a simplified manner.
VDD Data P-ch IN N-ch Output disable
VDD P-ch OUT
N-ch
Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) CMOS input buffer Type B Type E-B
V DD P.U.R. P.U.R. enable Data Output disable Type D IN/OUT P-ch
IN
Schmitt trigger input with hysteresis
Type A
P.U.R.: Pull-up resistor
Type B-C
VDD P.U.R. P.U.R. enable
P-ch
IN
P.U.R.: Pull-up resistor
7
PD75P068
(2/3)
Type F-A VDD P.U.R. P.U.R. enable Data Type D Output disable Data Output disable Type B N-ch P-ch P.U.R. enable Type M-C VDD P.U.R. P-ch
IN/OUT
IN/OUT
P.U.R.: Pull-up resistor Type F-B VDD P.U.R P.U.R. enable Output disable
(P)
P.U.R.: Pull-up resistor Type Y (For type Y-A , Y-D)
VDD IN VDD P-ch N-ch + Sampling C - AVSS AVSS Reference voltage (from voltage tap of serial resistor string) Input enable
P-ch VDD P-ch IN/OUT
Data Output disable Output disable (N) N-ch
P.U.R.: Pull-up resistor Type M-A Type Y-A 5
IN/OUT
IN instruction
Data Output disable
N-ch (Withstand voltage: +10 V)
Type A
Input buffer IN Type Y
Input buffer with an intermediate withstand voltage of +10 V
P.U.R.: Pull-up resistor
8
PD75P068
(3/3)
Type Y-D VDD P.U.R. AVREF P.U.R. enable Data Output disable Type D P-ch Type Z
IN/OUT
Reference voltage Type B
Type Y AVSS
P.U.R.: Pull-up resistor
2.
DIFFERENCE BETWEEN THE PD75P068 AND PD75068
The PD75P068 is produced by replacing the internal mask ROM (program memory) of the PD75068 with a one-time PROM in which data can be written once. Both have the same CPU function and internal hardware. Table 2-1 shows the difference between the PD75P068 and PD75068. For details of the CPU function and internal hardware, refer to the individual references for the PD75068. Table 2-1 Difference between the PD75P068 and PD75068
Item Program memory
PD75P068 (One-time PROM product)
* 0000H to 1F7FH * 8064 words x 8 bits
PD75P068 (Mask ROM product)
Pull-up resistor
Ports 0 to 3 and 6 Ports 4 and 5
Can be specified with software. None Contained Mask option Mask option 2.7 to 6.0 V P30/MD0 to P33/MD3 P30 to P33
XT1 feedback resistor Operating supply voltage range Pin function Pins 6 to 9 of SDIP Pins 23 to 26 of QFP Pin 20 of SDIP Pin 38 of QFP Electrical characteristics
VPP
IC
They differ in consumption current. For details, refer to the corresponding items in each data sheet. Since they differ in circuit scale and mask layout, they differ in noise immunity and noise radiation.
Others
Caution The PROM and mask ROM products differ in noise immunity and noise radiation. Use not ES products but CS products (mask ROM products) to evaluate them thoroughly when considering the change from the PROM products to the mask ROM products during processes from preproduction to volume production.
9
PD75P068
3. WRITING TO AND VERIFYING PROM (PROGRAM MEMORY)
The program memory in the PD75P068 is a one-time PROM which consists of 8064 words x 8 bits. Writing to and verifying the contents of the one-time PROM is accomplished using the pins shown in the table below. Note that address inputs are not used; instead, the address is updated using the clock input from the X1 pin.
Pin name VPP Function Voltage is applied to this pin when writing to the program memory or verifying its contents (normally VDD electric potential). Address update clock inputs used when writing to the program memory or verifying its contents. The X2 pin is used to input the inverted signal of the X1 pin input. Operation mode selection pins used when writing to the program memory or verifying its contents. I/O pins for 8-bit data used when writing to the program memory or verifying its contents. Power voltage is applied to this pin. During normal operation, 2.7 to 6.0 V should be applied; 6 V should be applied when writing to the program memory or verifying its contents.
X1, X2
MD0 to MD3 (P30 to P33) P40 to P43 (low-order four bits) P50 to P53 (high-order four bits) VDD
Caution Since the PD75P068CU/GB does not have an erasure window, the contents of the memory can not be erased with ultraviolet radiation.
3.1
OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY
If +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin, the PD75P068 enters program memory write/verify mode. The specific operating mode is then selected by setting the MD0 through MD3 pins as listed below. The remaining pins are all connected to VSS via pull-down resistors.
Operating mode specification VPP VDD MD0 H +12.5 V +6 V L L H x indicates L or H. MD1 L H L x MD2 H H H H MD3 L H H H Operating mode Program memory address clear mode Write mode Verify mode Program inhibit mode
10
PD75P068
3.2 (1) (2) (3) (4) (5) (6) (7) (8) (9) WRITING TO THE PROGRAM MEMORY Connect all unused pins to VSS through resistors. Apply a low-level signal to the X1 pin. Apply 5 V to VDD and VPP pins. Wait 10 s. Select program memory address clear mode. Apply +6 V to VDD and +12.5 V to VPP. Select program inhibit mode. Select write mode for 1 ms duration and write data. Select program inhibit mode. Select verify mode. If write is successful, proceed to step (10). If write fails, repeat steps (7) to (9).
The procedure for writing to program memory is described below; high-speed write is possible.
(10) Perform additional write for (Number (X) of repetitions of steps (7) to (9)) x 1 ms duration. (11) Select program inhibit mode. (12) Increment the program memory address by inputting four pulses on the X1 pin. (13) Repeat steps (7) to (12) until the last address is reached. (14) Select program memory address clear mode. (15) Apply 5 V to VDD and VPP pins. (16) Turn the power off. The timing for steps (2) to (12) is shown below.
Repeat X times
Write
Verify
Additional write
Address increment
VPP VPP VDD VDD +1 VDD
VDD
X1
P40-P43 P50-P53
Data input
Data output
Data input
MD0 (P30) MD1 (P31)
MD2 (P32) MD3 (P33)
11
PD75P068
3.3 READING THE PROGRAM MEMORY
The procedure for reading the contents of program memory is described below. The read is performed in the verify mode. (1) (2) (3) (4) (5) (6) (7) (8) (9) Connect all unused pins to VSS through resistors. Apply a low-level signal to the X1 pin. Apply 5 V to VDD and VPP pins. Wait 10 s. Select program memory address clear mode. Apply +6 V to VDD and +12.5 V to VPP. Select program inhibit mode. Select verify mode. Data is output sequentially one address at a time for each cycle of four clock pulses appearing on the X1 pin. Select program inhibit mode. Select program memory address clear mode.
(10) Apply 5 V to VDD and VPP pins. (11) Turn the power off. The timing for steps (2) to (9) is shown below.
VPP VPP VDD VDD +1 VDD VDD
X1
P40-P43 P50-P53
Data output
Data output
MD0 (P30)
MD1 (P31)
"L"
MD2 (P32)
MD3 (P33)
12
PD75P068
4. SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (PD75P068CU and PD75P068GB-3B4) due to their structure before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them and storing them at 125 C for 24 hours. NEC offers a charged service called QTOP microcomputer service. This service includes writing to onetime PROM, marking, screening, and verification. Ask your sales representative for details. 5
13
PD75P068
5. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Parameter Supply voltage Supply voltage Input voltage Symbol VDD VPP VI1 VI2 Output voltage High-level output current Low-level output current 1 pin of ports 2 and 6 VO IOH 1 pin All pins IOLNote 1 pin of ports 0, 3, 4, and 5 Peak value rms Peak value rms Total of all pins of ports 0, 3, 4, and 5 Total of all pins of ports 2, and 6 Operating temperature Storage temperature Topt Peak value rms Peak value rms Ports other than ports 4 and 5 Ports 4 and 5 N-ch open drain Conditions Rated value -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to +11 -0.3 to VDD + 0.3 -10 -30 30 15 20 5 160 120 30 20 -40 to +85 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C
Tstg
-65 to +150
C
Note Calculate rms with [rms] = [peak value] x duty. Caution Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values.
CAPACITANCE (Ta = 25 C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions f = 1 MHz 0 V for pins other than pins to be measured Min. Typ. Max. 15 15 15 Unit pF pF pF
14
PD75P068
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Ceramic resonator Recommended constant
VSS C1 X1 X2 C2
Parameter Oscillator frequency (fX) Note 1 Oscillation settling time
Note 2
Conditions
Min. 1.0
Typ.
Max. 5.0Note 3
Unit MHz
4
ms
Crystal
VSS C1
X1
X2 C2
Oscillator frequency (fX) Note 1 Oscillation settling time
Note 2
1.0
4.19
5.0Note 3
MHz
VDD = 4.5 to 6.0 V
10 30 1.0 5.0Note 3
ms ms MHz
External clock
X1
X2
X1 input frequency (fX) Note 1 X1 input high/low level width (tXH, tXL)
100
500
ns
PD74HCU04
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD is reaches the minimum voltage in the oscillation voltage range. 3. When 4.19 MHz < fX 5.0 MHz, do not select PCC = 0011 as the instruction execution time. When PCC = 0011, one machine cycle falls short of 0.95 s, the minimum value for the standard. Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. * Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator.
15
PD75P068
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Crystal Recommended constant
VSS XT1 XT2 R C3 C4
Parameter Oscillator frequency (fXT) Note 1 Oscillation settling time
Note 2
Conditions
Min. 32
Typ. 32.768
Max. 35
Unit kHz
VDD = 4.5 to 6.0 V
1.0
2 10
s s kHz
External clock
XT1
XT2
XT1 input frequency (fXT) Note 1 XT1 input high/low level width (tXTH, tXTL)
32
100
5
15
s
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD reaches the minimum voltage in the oscillation voltage range. Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. * Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VSS. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator.
16
PD75P068
RECOMMENDED CAPACITORS IN THE OSCILLATION CIRCUIT Main system clock: Ceramic resonator (Ta = -20 to +80C)
Recommended constant C1 (pF) 150 47 C2 (pF) 150 47 Oscillation voltage range Min. (V) Max. (V)
5
Manufacturer
Part number KBR-1000F/Y KBR-2.0MS PBRC 2.00A KBR-3.0MS KBR-3.58MSA PBRC 3.58A KBR-3.58MKS
Frequency (MHz) 1.00 2.00 3.00
33 3.58 Contained 33 4.00 Contained
33
Kyocera
KBR-3.58MWS KBR-4.00MSA PBRC 4.00A KBR-4.00MKS KBR-4.00MWS KBR-5.0MSA PBRC 5.00A KBR-5.0MKS KBR-5.0MWS CRHF2.50 2.50
Contained 2.7 33 6.0
Contained
33 5.00 Contained
33
Contained
Toko
CRHF4.19 CRHT4.19 CRHF5.00
30 4.19 5.00 Contained 30
30 Contained 30 2.7 6.0
Main system clock: Crystal (Ta = -40 to +85C)
Recommended constant C1 (pF) C2 (pF) Oscillation voltage range Min. (V) Max. (V)
Manufacturer
Part number
Frequency (MHz) 2.00
Kinseki
HC-49/U
4.19 6.00
22
22
3.5
6.0
Subsystem clock: Crystal (Ta = -15 to +60C)
Recommended constant C3 (pF) 15 C4 (pF) 27 R (k) 220 Oscillation voltage range Min. (V) 2.7 Max. (V) 6.0
Manufacturer Kyocera
Part number KF-38G
Frequency (kHz) 32.768
17
PD75P068
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 VIH4 Low-level input voltage VIL1 VIL2 VIL3 High-level output voltage Low-level output voltage VOH Ports 2, 3, and 11 Ports 0, 1, and 6, and RESET Ports 4 and 5 X1, X2, XT1, and XT2 Ports 2 to 5 and 11 Ports 0, 1, and 6, and RESET X1, X2, XT1, and XT2 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A VOL Ports 4 and 5 Port 3 VDD = 4.5 to 6.0 V, IOL = 15 mA VDD = 4.5 to 6.0 V, IOL = 15 mA Conditions Min. 0.7VDD 0.8VDD 0.7VDD VDD - 0.5 0 0 0 VDD - 1.0 VDD - 0.5 0.7 0.8 2.0 2.0 0.4 0.5 Pull-up resistor: 1 k or more Other than X1, X2, XT1, and XT2 X1, X2, XT1, and XT2 VI = 10 V VI = 0 V Ports 4 and 5 Other than X1, X2, XT1, and XT2 X1, X2, XT1, and XT2 VO = VDD VO = 10 V VO = 0 V VDD = 5.0 V 10 % VDD = 3.0 V 10 % Ports 4 and 5 0.2VDD 3 20 20 -3 -20 3 20 -3 Typ. Max. VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V V V V
VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A SB0 and SB1 High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current High-level output leakage current Low-level out-put leakage current Built-in pull-up resistor ILIL1 ILIL2 ILOH1 ILOH2 ILOL VI = VDD
A A A A A A A A
k k mA mA
RU
P01, P02, P03, and ports 1 to 3, and 6 VI = 0 V
15 30
40
80 300
Power supply currentNote 1
IDD1
IDD2
VDD = 5.0 V 10 %Note 3 4.19 MHzNote 2 crystal resonance VDD = 3.0 V 10 %Note 4 C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10 % VDD = 3.0 V 10 %
3.3 0.45 600 220 35 5 0.5 0.1
10 1.4 1800 700 120 15 20 10 5
A A A A A A A
IDD3 IDD4 IDD5
32.768 kHzNote 5 VDD = 3.0 V 10 % crystal resonance HALT mode VDD = 3.0 V 10 % XT1 = 0 V VDD = 5.0 V 10 % VDD = 3.0 V 10 % Ta = 25 C
0.1
Notes 1. 2. 3. 4. 5.
This current excludes the current which flows through the built-in pull-up resistors. This value applies also when the subsystem clock oscillates. Value when the processor clock control register (PCC) is set to 0011 and the PD75036 is operated in the high-speed mode Value when the PCC is set to 0000 and the PD75036 is operated in the low-speed mode This value applies when the system clock control register (SCC) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse.
18
PD75P068
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
Parameter CPU clock cycle time (minimum instruction execution time = 1 machine cycle)Note 1 TI0 input frequency
Symbol tCY
Conditions Operated by main system clock pulse VDD = 4.5 to 6.0 V
Min. 0.95 3.8 114 0 0
Typ.
Max. 64 64
Unit
s s s
MHz kHz
Operated by subsystem clock pulse fTI VDD = 4.5 to 6.0 V
122
125 1 275
TI0 input high/low level width Interrupt input high/ low level width
tTIH, tTIL tINTH, tINTL
VDD = 4.5 to 6.0 V
0.48 1.8
s s s s s s
INT0 INT1, INT2, and INT4 KR0 to KR3
Note 2
10 10 10
RESET low level width
tRSL
Notes 1. The cycle time of the CPU clock () depends on the connected resonator frequency, the system clock control register (SCC), and the processor clock control register (PCC). The figure on the right side shows the cycle time tCY characteristics for the supply voltage VDD during main sysCycle time tCY [ s]
6 5 4 3 64 60 70
tCY vs VDD
(Main system clock in operation)
Operation guaranteed range
tem clock operation. 2. This value becomes 2tCY or 128/fX according to the setting of the interrupt mode register (IM0).
2
1
0.5 0 1 2 3 4 5 6
Power supply voltage VDD [V]
19
PD75P068
SERIAL TRANSFER OPERATION Two-wire and three-wire serial I/O modes (SCK ... Internal clock output):
Parameter SCK cycle time
Symbol tKCY1
Conditions VDD = 4.5 to 6.0 V
Min. 1600 3800
Typ.
Max.
Unit ns ns ns ns ns
SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) Delay time from SCK to SO output
tKL1 tKH1 tSIK1
VDD = 4.5 to 6.0 V
tKCY1/2 - 50 tKCY1/2 - 150 150
tKSI1
400
ns
tKSO1
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0
250 1000
ns ns
Two-wire and three-wire serial I/O modes (SCK ... External clock input):
Parameter SCK cycle time
Symbol tKCY2
Conditions VDD = 4.5 to 6.0 V
Min. 800 3200
Typ.
Max.
Unit ns ns ns ns ns
SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) Delay time from SCK to SO output
tKL2 tKH2 tSIK2
VDD = 4.5 to 6.0 V
400 1600 100
tKSI2
400
ns
tKSO2
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0
300 1000
ns ns
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
20
PD75P068
SBI mode (SCK ... Internal clock output (master)):
Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V Min. 1600 3800 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) Delay time from SCK to SB0/SB1 output From SCK to SB0/SB1 From SB0/SB1 to SCK SB0/SB1 low level width SB0/SB1 high level width tKL3 tKH3 tSIK3 VDD = 4.5 to 6.0 V tKCY3/2 - 50 tKCY3/2 - 150 150 Typ. Max. Unit ns ns ns ns ns
tKSI3
tKCY3/2
ns
tKSO3
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0 tKCY3 tKCY3 tKCY3 tKCY3
250 1000
ns ns ns ns ns ns
tKSB tSBK tSBL tSBH
SBI mode (SCK ... External clock input (slave)):
Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 4.5 to 6.0 V Min. 800 3200 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) Delay time from SCK to SB0/SB1 output From SCK to SB0/SB1 From SB0/SB1 to SCK SB0/SB1 low level width SB0/SB1 high level width tKL4 tKH4 tSIK4 VDD = 4.5 to 6.0 V 400 1600 100 Typ. Max. Unit ns ns ns ns ns
tKSI4
tKCY4/2
ns
tKSO4
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0 tKCY4 tKCY4
300 1000
ns ns ns ns
tKSB tSBK
tSBL tSBH
tKCY4 tKCY4
ns ns
Note RL and CL are the resistance and capacitance of the SB0/SB1 output line load respectively.
21
PD75P068
A/D CONVERTER (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter Resolution
Absolute accuracyNote 1
Symbol
Conditions
Min. 8
Typ. 8
Max. 8 1.5 2.0 168/fX 44/fX
Unit bit LSB LSB
2.5 V AVREF VDDNote 2 -10 Ta +85C -40 Ta < -10C
Conversion timeNote 3 Sampling timeNote 4 Reference input voltage Analog input voltage Analog input impedance AVREF current
tCONV tSAMP AVREF VIAN RAN 2.5 AVSS 1000
s s
V V M
VDD AVREF
AIREF
0.7
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (1/2 LSB) 2. 2.5 V AVREF VDD ADM1 is set to 0 or 1 depending on the A/D converter reference voltage (AVREF) as follows:
2.5 V AVREF
0.6VDD
0.65VDD
VDD (2.7 to 6.0 V)
ADM1 = 0 ADM1 = 1
When 0.6VDD AVREF 0.65VDD, ADM1 can be set to either 0 or 1. 3. Time from the execution of a conversion start instruction till the end of conversion (EOC = 1) (40.1 s: fX = 4.19 MHz) 4. Time from the execution of a conversion start instruction till the end of sampling (10.5 s: fX = 4.19 MHz)
22
PD75P068
AC Timing Measurement Points (Excluding X1 and XT1 Inputs)
0.8VDD 0.2VDD
Measurement points
0.8VDD 0.2VDD
Clock Timing
1/fX tXL tXH
VDD - 0.5 V X1 input 0.4 V
1/fXT tXTL tXTH
VDD - 0.5 V XT1 input 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
23
PD75P068
Serial Transfer Timing Three-wire serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
Two-wire serial I/O mode:
tKCY2 tKL2 tKH2
SCK
tSIK2
tKSI2
SB0 and SB1
tKSO2
24
PD75P068
Serial Transfer Timing Bus release signal transfer:
tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4
tKSB
tSBL
tSBH
tSBK
SB0 and SB1 tKSO3 tKSO4
Command signal transfer:
tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4
tKSB
tSBK
SB0 and SB1 tKSO3 tKSO4
Interrupt Input Timing
tINTL INT0, INT1, INT2 and INT4 KR0-KR3
tINTH
RESET Input Timing
tRSL
RESET
25
PD75P068
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (Ta = -40 to +85 C)
Parameter Data hold supply voltage
Data hold supply currentNote 1
Symbol VDDDR IDDDR tSREL tWAIT VDDDR = 2.0 V
Conditions
Min. 2.0
Typ.
Max. 6.0
Unit V
0.1 0
10
A s
Release signal setting time
Oscillation settling timeNote 2
Release by RESET Release by interrupt request
2 /fX
Note 3
17
ms ms
Notes 1. 2. 3.
Excluding the current which flows through the built-in pull-up resistors CPU operation stop time for preventing unstable operation at the beginning of oscillation This value depends on the settings of the basic interval timer mode register (BTM) shown below.
Wait time (Values at fX = 4.19 MHz in parentheses) 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
Data Hold Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Data hold mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode STOP mode Data hold mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (Interrupt request)
tWAIT
26
PD75P068
6. CHARACTERISTIC CURVES (FOR REFERENCE)
IDD vs VDD (When the main system clock operates at 4.19 MHz with a crystal)
(Ta = 25 C)
5
5.0
X1 Crystal 4.19 MHz
X2
XT1 Crystal 32.768 kHz
XT2
PCC = 0011
330 k
3.0 PCC = 0010
22 pF 22 pF 18 pF 18 pF
PCC = 0000 1.0 Main system clock HALT mode + 32 kHz oscillation
0.5
Supply current IDD (m A)
0.1
Subsystem clock operating mode
0.05 Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode
0.01
0.005
0.001 0 2 4 Supply voltage VDD (V) 6 8
27
PD75P068
IDD vs VDD (When the main system clock operates at 2.0 MHz with a crystal)
(Ta = 25 C)
5.0
X1 Crystal 2.0 MHz
X2
XT1 Crystal 32.768 kHz
XT2
330 kW
3.0 PCC = 0011 PCC = 0010 1.0 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation
22 pF
22 pF
18 pF
18 pF
0.5
Supply current IDD (m A)
0.1
Subsystem clock operating mode
0.05 Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode
0.01
0.005
0.001 0 2 4 Supply voltage VDD (V) 6 8
28
PD75P068
IDD vs VDD (When the main system clock operates at 4.19 MHz with a ceramic resonator)
(Ta = 25 C)
5.0
X1 Ceramic resonator 4.19 MHz
X2
XT1 Crystal 32.768 kHz
XT2
PCC = 0011
330 kW
3.0
PCC = 0010
30 pF 30 pF 18 pF 18 pF
PCC = 0000 1.0 Main system clock HALT mode + 32 kHz oscillation
0.5
Supply current IDD (m A)
0.1
Subsystem clock operating mode
0.05 Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode
0.01
0.005
0.001 0 2 4 Supply voltage VDD (V) 6 8
29
PD75P068
IDD vs VDD (When the main system clock operates at 2.0 MHz with a ceramic resonator)
(Ta = 25 C)
5.0
X1 Ceramic resonator 2.0 MHz
X2
XT1 Crystal 32.768 kHz
XT2
330 kW
3.0
PCC = 0011
30 pF 30 pF 18 pF 18 pF
PCC = 0010 1.0
PCC = 0000 Main system clock HALT mode + 32 kHz oscillation
0.5
Supply current IDD (m A)
0.1
Subsystem clock operating mode
0.05 Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode
0.01
0.005
0.001 0 2 4 Supply voltage VDD (V) 6 8
30
PD75P068
IDD vs fx 3.0 X1 2.5 X2 (VDD = 5 V, Ta = 25 C) 1.0 X1 X2 IDD vs fx (VDD = 3 V, Ta = 25 C)
PCC = 0011
2.0
PCC = 0010 PCC = 0010
IDD (mA)
IDD (mA)
1.5
0.5
PCC = 0011 PCC = 0000
1.0 PCC = 0000 Main system clock HALT mode 0.5 Main system clock HALT mode
0 0
1
2
3 fX (MHz)
4
5
6
0 0
1
2
3 fX (MHz)
4
5
6
IOL vs VOL (Port 0) 40 (Ta = 25 C) 30
IOL vs VOL (Ports 2 and 6) (Ta = 25 C)
25 VDD = 6 V 30 VDD = 5 V VDD = 4 V 20 VDD = 6 V VDD = 5 V VDD = 4 V
IOL (mA)
IOL (mA)
20
15
VDD = 3 V
VDD = 3 V 10 VDD = 2.7 V 10 5
VDD = 2.7 V
0 0
1
2 VOL (V)
3
4
5
0 0
1
2 VOL (V)
3
4
5
31
PD75P068
IOL vs VOL (Port 3) 40 (Ta = 25 C) 40 IOL vs VOL (Ports 4 and 5) (Ta = 25 C)
VDD = 5 V 30 VDD = 6 V VDD = 4 V 30 VDD = 6 V VDD = 5 V VDD = 4 V
IOL (mA)
IOL (mA)
20
VDD = 3 V
20
VDD = 3 V
VDD = 2.7 V VDD = 2.7 V
10
10
0 0
1
2 VOL (V)
3
4
5
0 0
1
2 VOL (V)
3
4
5
IOH vs VOH 15 (Ta = 25 C)
VDD = 5 V 10 VDD = 6 V VDD = 4 V
IOH (mA)
VDD = 3 V
5
VDD = 2.7 V
0 0
1
2 3 VDD - VOH (V)
4
5
32
PD75P068
7. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42 22
1 A
21
K L
I G J H
F C D N
M
B M
R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15
INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15 P42C-70-600A-1
33
PD75P068
44 PIN PLASTIC QFP ( 10)
A B
33 34
23 22
detail of lead end
C
D
S
44 1
12 11
F
G
H
IM
J K
P
N L P44GB-80-3B4-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 13.6 0.4 10.0 0.2 10.0 0.2 13.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.535+0.017 -0.016 0.394+0.008 -0.009 0.394+0.008 -0.009 0.535+0.017 -0.016 0.039 0.039 0.014+0.004 -0.005 0.006 0.031 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX.
34
M
55
Q
PD75P068
8. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the PD75P068. For details of the recommended soldering conditions, refer to our document "SMD Surface Mount Technology Manual" (IEI-1207). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. 5
Table 8-1 Soldering Conditions for Surface-Mount Devices
PD75P068GB-3B4: 44-pin plastic QFP (10 x 10 mm)
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (at 210 C or more) Maximum allowable number of reflow processes: 2 (1) Do not start reflow-soldering the device if its temperature is higher than the room temperature because of a previous reflow soldering. (2) Do not use water for flux cleaning before a second reflow soldering. Peak package's surface temperature: 215 C Reflow time: 40 seconds or less (at 200 C or more) Maximum allowable number of reflow processes: 2 (1) Do not start reflow-soldering the device if its temperature is higher than the room temperature because of a previous reflow soldering. (2) Do not use water for flux cleaning before a second reflow soldering. Solder temperature: 260C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature: 120 max. (measured on the package surface) Terminal temperature: 300 C or less Flow time: 3 seconds or less (for each side of device) Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating method
-
Caution Do not apply more than a single process at once, except for "Partial heating method."
Table 8-2
Soldering Conditions for Through Hole Mount Devices
PD75P068CU: 42-pin plastic shrink DIP (600 mil)
Soldering process Wave soldering (only for leads) Partial heating method Soldering conditions Solder temperature: 260 C or less Flow time: 10 seconds or less Terminal temperature: 260 C or less Flow time: 10 seconds or less
Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does not come in contact with the main body of the package. Notice Other versions of the products are available. For these versions, the recommended reflow soldering conditions have been mitigated as follows: Higher peak temperature (235 C), two-stage, and longer exposure limit. Contact an NEC representative for details.
35
PD75P068
APPENDIX A DEVELOPMENT TOOLS
The following development tools are provided for developing systems including the PD75P068:
IE-75000-RNote 1 IE-75001-R IE-75000-R-EMNote 2 Hardware EP-75068CU-R EP-75068GB-R EV-9200G-44 PG-1500 PA-75P008CU IE control program Software PG-1500 controller RA75X relocatable assembler
In-circuit emulator for the 75X series
Emulation board for the IE-75000-R and IE-75001-R Emulation probe for the PD75P068CU Emulation probe for the PD75P068GB. A 44-pin conversion socket, the EV-9200G-64, is attached to the probe. PROM programmer PROM programmer adapter for the PD75P068CU/GB. Connected to the PG-1500. Host machine * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3) * PC/ATTM series (PC DOSTM Ver. 3.10)
Notes 1. Maintenance service only 2. Not contained in the IE-75001-R 3. MS-DOS versions 5.00 and 5.00A are provided with a task swap function. This function, however, cannot be used in these software. Remark Refer to 75X Series Selection Guide (IF-1027) for development tools manufactured by third parties.
36
PD75P068
APPENDIX B RELATED DOCUMENTS
Documents related to the device
Document Name User's Manual Application Note (Preliminary) 75X Series Selection Guide Document No. IEU-1366 IEA-1296 IF-1027
Documents related to development tools
Document Name IE-75000-R/IE-75001-R User's Manual IE-75000-R-EM User's Manual Hardware EP-75068CU-R User's Manual EP-75068GB-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual Document No. EEU-1455 EEU-1294 EEU-1317 EEU-1428 EEU-1335 EEU-1346 EEU-1363 EEU-1291
Other documents
Document Name Package Manual SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Document No. IEI-1213 IEI-1207 IEI-1209 IEI-1203 IEI-1201 MEI-1202
Caution The above documents may be revised without notice. Use the latest versions when you design an application system.
37
PD75P068
[MEMO]
38
PD75P068
Cautions on CMOS Devices
1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. 2 CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate-level input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. 3 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first.
39
PD75P068
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92. 6
MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.

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